1. Field of the Invention
The present invention relates to nodes for switching a number of data channels and is particularly concerned with nodes in digital networks used to switch multiplexed low speed data channels.
2. Description of Related Art
Within a high bandwidth digital channel, it is potentially possible to provide a large number of data channels at rates as low as 400 bits per second. However at the node where the low speed data channels are interfaced with the rest of the network it is necessary to provide a multiplexer for switching data between selected channels and the network. In practice conventional multiplexer designs constitute a bottleneck which prevents the full channel-carrying potential of the network from being realised. If the main data path of the network has a bandwidth, for example, of tens of kilobits per second and the low speed data paths have bandwidths of hundreds of bits per second then it would be theoretically possible to interface as many as 100 of the low speed data channels to the network via a single node. Conventional matrix switches used in multiplexers are essentially serial devices and so the multiplexer needs to function with the same high bandwidth as the main data path. Known multiplexer designs, e.g. as disclosed in EP-A-0186141 and U.S. Pat. No. 4,658,152, are inefficient in handling and switching large numbers of data channels at the high speeds which would be required in practice to provide this sort of bandwidth. In the designs of these prior art documents, data in multiplexed frames is received at a high speed data interface circuit for distribution to a number of low speed interface circuits. A translation map is addressed with the sequence number of the incoming data byte to retrieve the address (identity) of the low speed interface circuit and the data is placed on a common bus together with the destination address. In the reverse direction the map is addressed with the sequence number of the outgoing data byte to obtain the identity of the source interface circuit. This identity is placed on the bus to command the source circuit to place its data byte on the bus for receipt and assembly into a frame for transmission by the high speed interface circuit.